Standard Protocols
Advanced Techniques
Under development
General Advice
Inspiration
Standard Protocols
Advanced Techniques
Under development
General Advice
Inspiration
We use labview programs to control voltage sources and acquire data. For documentation on the MeaSureit program see Vera's program development site. It is straightforward to use programs that are already written. If you need to write your own labview program, it will take some time investment to learn this graphical programming language. The time is well spent because labview the industry standard for software control of processes. There are tutorials, videos and exercises on the labview website and further material at labview for students section. On the T: drive there is a folder Manuals/Labview where we keep some example programs.
More information:
Nanotubes burn up like a fuse if currents get too high (above 10 microAmps in a single tube starts to be dangerous). If the gate oxide is stressed, it can also be irreversibly damaged. This can happen several ways.
To collect quality data at fast sampling rates there are many points to consider
Three ways to apply a gate voltage to a silicon/silicon oxide chip:
It is important to sweep the gate voltage in a continuous fashion, rather than instantaneous jumps. Fast switching puts stress on the insulating dielectric (the silicon oxide). If the insulating dielectric breaks down, large currents will start leaking between the gate and the top electrodes.
If you put a positive bias on the nanotube, the current throught the tube should always be positive. If you see negative currents as you sweep the gate voltages, something is suspicious. Three possibilities
Using a top gate is a convenient way to obtain an I(Vg) measurement from a device with (1) no 'back gate' (such as quartz) or (2) with damaged gate oxides. Over time, leakage through the gate oxide will become significant. A common cause of this is when metal nanotube catalyst 'diffuses' into the oxide layer (timescales ~ weeks/months), forming conductive 'filaments' through the oxide. In this case, I(Vg) curves can still be obtained by using a top gate. The top gate has a lower capacitive coupling to the devices compared to a built-in back gate. The rule of thumb is ±10 V on the back gate corresponds to about ±30 V on the top gate (empirical estimate using 300 nm oxide) .
Important: Be sure that the silver paint area does not overlap any electrodes underneath. Ions in the paint will diffuse through the top gate chip over time, forming conductive 'filaments' that lead to top gate leakage. If you are sure to follow this step, top gate ranges ±100 V should be easily achievable.
The current through a CNT or graphene device will always fluctuate due to 1/f noise. This noise is intrinsic to any electrical measurement we perform. However, other types of noise which are unrelated to the device need to be minimized. External noise sources typically show up as spikes in the power spectral density of current fluctuations. In the most extreme cases, you can actually see sinusoidal oscillations in your current measurement.
The most common reason for unusually high noise can be fixed by connecting the shield on the BNC wires which carry source, drain and gate signals (see Figure below).
This walkthrough describes how to set up a fluid cell for use with a PDMS stamp and and on-chip liquid gate electrode.
Jaan Mannik developed the following local liquid gate technique:
Tubing is secured to the arm of a micromanipulator. A thin Pt wire is inserted into the tubing. The wire comes out of the tube after passing through a T-junction. The wire inside the tubing is called the working electrode. A voltage is applied to the working electrode using the DAQ.
A second Pt wire is on the outside of the tubing. This is called the reference electrode. This outer Pt wire can be used to record the actual potential of the liquid (sometimes it is different than the voltage applied to the working electrode). The voltage signal can be sent straight to the DAQ.
A 'megasweep' is when you scan the source-drain voltage (Vsd) and gate voltage (Vg) while recording current (I) through the device. This allows you to make a three dimensional plot, usually with Vsd on the y-axis, Vg on the x-axis, & conductance or the differential conductance (dI/dVsd) on the z-axis.
When the scan is finished…