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====== Silicon wafers ======

We current use p+ doped silicon, [1 0 0] with 200 nm thermally grown oxide. The [1 0 0] refers to the crystallographic axis of the vector normal to the surface. [1 0 0] wafers will break into squares.

In March 2024 we ordered a batch of wafers from Nova: P-type (boron) 0.01-0.02 ohm-cm; 300 nm wet thermal oxide; Prime grade. The resistivity is below 0.04 ohm-cm, which indicates "degenerately doped" silicon. Degenerate doping will remain conducting even below 1 kelvin.

There are 3 wafer grades: test (lowest grade), prime and epi (highest grade).

Epi is short for epitaxial, which means that after the ignot has been sawn and polished into wafers an additional layer of silicon grown, one atomic layer at time, to ensure that the surface is perfectly flat.

McEuen group used to order degenerately doped wafers from Nova Wafers (Texas-based, friendly people): These were prime wafers with Si resistivity between 1 and 3 mOhms-cm (this is overkill, lower resistance than we need). The Columbia nanoscience group uses wafers with resistivity of 10 to 50 Ohms-cm; choice of resistance depends how far down in temperature you want to go before the backgate freezes out. 

One Engineering Prof. told me test wafers are just not good enough for making Si devices but should be fine for everything else. However, a typically a test wafer will come out of a batch where something went wrong and it could be anything (scratch, dopant, etc.). The catch is that they are way cheaper than Prime grade. Columbia has ordered some Test wafers from Si-Tech lately and have been happy.

The quality of the oxide (chance of breakdown or pinholes) has little to do with the type of wafer. They have to send the cassette to a cleanroom to have the wet thermal oxide grown and it could be a fault of the process used or the facility used. Members of McEuen group used to complain when they saw by eye that some batches from Nova had visible inhomogeneity in oxide thickness. Philip Kim also had a bad batch from Nova and stopped using them. 

For thinner oxides (less than 100 nm?), some companies offer a "dry oxide" process. Dry oxide grows more slowly, so it is more expensive. The dry process can improve the breakdown field, and reduce the chance of pin holes. 

Philip Kim's approach: (might not be available anymore due to cuts in federal funding) Buy wafers from Mems-exchange. They allow you to buy as few wafers as you want, you can choose all the parameters in the process and the facility to be used. That way, he would try around some recipes for a few wafers at a time until finding something he was happy with, then buy in batches of 10 or so every time. It costs considerably more money but he gets better yield of good wafers and doesn't waste the money on 25 bad wafers if the bacth happens to be bad.