User Tools

Site Tools


silicon_wafers

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision
Previous revision
silicon_wafers [2019/09/09 21:26] ethanminotsilicon_wafers [2024/03/19 15:50] (current) ethanminot
Line 2: Line 2:
  
 We current use p+ doped silicon, [1 0 0] with 200 nm thermally grown oxide. The [1 0 0] refers to the crystallographic axis of the vector normal to the surface. [1 0 0] wafers will break into squares. We current use p+ doped silicon, [1 0 0] with 200 nm thermally grown oxide. The [1 0 0] refers to the crystallographic axis of the vector normal to the surface. [1 0 0] wafers will break into squares.
 +
 +In March 2024 we ordered a batch of wafers from Nova: P-type (boron) 0.01-0.02 ohm-cm; 300 nm wet thermal oxide; Prime grade. The resistivity is below 0.04 ohm-cm, which indicates "degenerately doped" silicon. Degenerate doping will remain conducting even below 1 kelvin.
  
 There are 3 wafer grades: test (lowest grade), prime and epi (highest grade). There are 3 wafer grades: test (lowest grade), prime and epi (highest grade).
Line 12: Line 14:
  
 The quality of the oxide (chance of breakdown or pinholes) has little to do with the type of wafer. They have to send the cassette to a cleanroom to have the wet thermal oxide grown and it could be a fault of the process used or the facility used. Members of McEuen group used to complain when they saw by eye that some batches from Nova had visible inhomogeneity in oxide thickness. Philip Kim also had a bad batch from Nova and stopped using them.  The quality of the oxide (chance of breakdown or pinholes) has little to do with the type of wafer. They have to send the cassette to a cleanroom to have the wet thermal oxide grown and it could be a fault of the process used or the facility used. Members of McEuen group used to complain when they saw by eye that some batches from Nova had visible inhomogeneity in oxide thickness. Philip Kim also had a bad batch from Nova and stopped using them. 
 +
 +For thinner oxides (less than 100 nm?), some companies offer a "dry oxide" process. Dry oxide grows more slowly, so it is more expensive. The dry process can improve the breakdown field, and reduce the chance of pin holes. 
  
 Philip Kim's approach: (might not be available anymore due to cuts in federal funding) Buy wafers from Mems-exchange. They allow you to buy as few wafers as you want, you can choose all the parameters in the process and the facility to be used. That way, he would try around some recipes for a few wafers at a time until finding something he was happy with, then buy in batches of 10 or so every time. It costs considerably more money but he gets better yield of good wafers and doesn't waste the money on 25 bad wafers if the bacth happens to be bad.  Philip Kim's approach: (might not be available anymore due to cuts in federal funding) Buy wafers from Mems-exchange. They allow you to buy as few wafers as you want, you can choose all the parameters in the process and the facility to be used. That way, he would try around some recipes for a few wafers at a time until finding something he was happy with, then buy in batches of 10 or so every time. It costs considerably more money but he gets better yield of good wafers and doesn't waste the money on 25 bad wafers if the bacth happens to be bad. 
silicon_wafers.1568089582.txt.gz · Last modified: 2019/09/09 21:26 by ethanminot